Physical Design Engineer

Role Overview

AMD is looking for a motivated and detail-oriented Physical Design Library Engineer to join our VLSI backend team. This role sits at the intersection of library management using CAD supported tools and AI-driven automation, playing a critical enabling function for Front End & Back End teams. You will own the end-to-end library delivery pipeline and leverage AI-powered tools to improve efficiency.

Responsibilities

• Own and execute the LibBuilder flow for standard cell and memory library generation.
• Drive MemView generation for memory compiler outputs across multiple PVT corners and process nodes.
• Maintain library quality across NDM, Liberty (.lib), LEF, and timing model deliverables.
• Track and manage PVT corner coverage including SS, FF, TT, low voltage, and high temperature.
• Serve as the primary point of contact for library-related issues raised by tile and block owners.
• Coordinate with CAD teams, foundries, and IP vendors to resolve library blockers.
• Perform debug of library generation failures in lib characterization and corner mapping.
• Develop and maintain AI-generated dashboards for library health and flow status.
• Automate repetitive library tasks using AI and scripting.

Requirements

• 4+ years of experience in Physical Design.
• Strong knowledge of Timing concepts.
• Proficiency with file formats such as LEF, DEF, and OASIS.
• Bachelor’s or Master’s degree in a related discipline preferred.

Skills

• LibBuilder
• Liberty (.lib)
• NDM
• Python/Scripting
• AI-assisted tools