Physical Design Engineer

Role Overview

Axiado is looking for a motivated and hands-on Physical Design Engineer to join our ASIC team. This role involves working across multiple aspects of backend implementation, including floorplanning, placement, CTS, routing, timing closure, power optimization, and physical signoff, while collaborating closely with experienced engineers across the ASIC development flow.

Responsibilities

• Participate in block-level and subsystem-level implementation from netlist to GDS.
• Perform floorplanning, placement, CTS, routing, and physical optimization activities.
• Analyze and resolve timing, congestion, utilization, and routing issues.
• Support ECO implementation and timing closure activities.
• Perform setup and hold timing analysis using PrimeTime or equivalent STA tools.
• Support DRC, LVS, ERC, Antenna, and density closure activities using Calibre and/or ICV.
• Analyze power, performance, and area (PPA) tradeoffs.
• Develop and maintain Tcl/Python scripts to improve flow efficiency.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 2–5 years of ASIC Physical Design experience.
• Experience with at least one successful tapeout or advanced-stage implementation project.
• Hands-on experience in Floorplanning, Placement, CTS, Routing, Timing Closure, and Physical Verification.

Skills

• Cadence Innovus
• Synopsys ICC2
• PrimeTime
• Tcl
• Python