ASIC Engineer :: Physical Design

Role Overview

Come join the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry. Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Responsibilities

As a member of the Physical Design team in Bangalore, India, you will be involved in creating next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place& route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.

Requirements

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with 8+ Years of exp
• All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
• Hierarchical design implementation approach, Timing closure, physical convergence.
• Power Integrity Analysis
• Experience with large designs ( >100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
• Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
• Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
• Good understanding of different CTS strategies and providing the feedback to Implementation Team.
• Drive methodologies and “best known methods” to streamline and automate physical design work.
• STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
• Good at Timing ECO Implementation strategy development/convergence. Experience in enabling the Tweaker/Primetime based ECO flows.
• Work on Automation scripts within STA tools for Methodology development. Excellent debugging skills in implementation issues and ability to produce creative solutions.
• Evaluate multiple timing methodologies/tools on different designs and technology nodes.