VLSI / ASIC Design Engineers Intern

Role Overview

We are looking for talented VLSI Engineers to join our team across ASIC Frontend, RTL Design, and Backend / Physical Design. This internship offers the opportunity to work on real-world projects and gain exposure to the complete RTL-to-GDSII design flow.

Responsibilities

• Perform ASIC Frontend Design and RTL Coding.
• Execute Physical Design implementation and DFT.
• Manage RTL-to-GDSII flows and Physical Verification.
• Develop and automate VLSI flows using scripting.
• Integrate ASIC design flows from Frontend to Backend.

Requirements

• Strong understanding of digital design concepts.
• Knowledge of PnR, timing, and physical verification flows.
• Ability to work in person.

Skills

• Verilog
• UVM
• Python
• TCL
• RTL Design

Benefits

• Work on real-world ASIC/VLSI projects.
• Exposure to complete RTL-to-GDSII design flow.
• Monthly pay starting from ₹35,000.00.