Engineer I

Role Overview

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. This role involves engaging in the logic design and verification of digital IPs, CPUs, peripherals, and sub-systems across various VLSI domains.

Responsibilities

• Engage in the logic design and verification of digital IPs, CPUs, peripherals, and sub-systems across various VLSI domains.
• Create and implement innovative designs and testbenches that are highly scalable, configurable, and efficient.
• Develop and implement UVM testbenches.

Requirements

• Minimum of 1+ years of experience with Bachelor's or Master's in Engineering.
• Solid understanding of electrical engineering concepts, Digital Electronics, and VLSI design concepts.
• Excellent communication, problem-solving and analytical skills.
• Ability to work independently and in a team.
• Good understanding in one or more of the following areas: Computer architecture, Logic design, Circuit design and semiconductor devices, Programming languages, or Hardware Description Languages.

Skills

• SystemVerilog
• Verilog
• Python
• C++
• UVM